Computers can be classified into complex instruction set computers (CISC) and reduced instruction set computers (RISC). The CISC machines conveniently read instruction words with variable length (e.g., 8 bit to 64 bit) in a single software program, wherein the RISC machines often read instruction words with constant length (e.g., 32 bit). The number of possible bit combinations which form the instruction words is often high for CISC and low for RISC. Among others, these features make RISC especially suitable for the integration of processor and memory into a single chip in embedded systems. However, a software program written for RISC may require more memory space than a software program with the same function which runs on a CISC machine.
To save memory space, instructions are conveniently stored in compressed form wherein code portions have variable lengths. However, such systems need real time converters to expand the instructions prior to execution. The present invention seeks to provide a converter which provides a high decoding rate for such instructions.